1. Field of the Invention
The present invention relates to a charge transfer element and in particular to a structure of an output section which enhances output sensitivity.
2. Description of the Related Art
FIG. 7 shows a structure of a CCD solid state image capturing element of a frame transfer type. A CCD solid state image capturing element of a frame transfer type comprises an image capturing section 10i, a storage section 10s, a horizontal transfer section 10h, and an output section 10d. The image capturing section 10i generates information charge and transfers to the subsequent storage section 10s to store therein using a charge transfer element which is a CCD shift register. Besides being stored in the storage section 10s, the information charge is also transferred to the subsequent horizontal transfer section 10h in units of one line and further to the output section 10d in units of one pixel. The output section 10d converts the information charge of an amount for each pixel into a voltage value, and variation of the voltage values is output as a CCD output.
A floating diffusion (capacitive) region having a capacitance for temporary storage of information charge is provided on the output side of the channel region of the horizontal transfer section 10h, and potential variation caused by the charge stored in the capacity is extracted as an output signal. The potential value of an output signal is determined by dividing the amount of the stored information charge by the capacitance value of the floating diffusion region. Reduction of the capacitance value of the floating diffusion region enables enhancement of the output sensitivity of the solid state image capturing element.
FIG. 8 is a diagram showing an equivalent circuit of the output section 10d, and FIG. 9 is a plan view showing a structure of the horizontal transfer section 10h and the output section 10d. 
As shown in FIG. 8, the output section 10d basically comprises three output transistors Td1, Td2, Td3 and three load transistors Ta1, Ta2, Ta3. The output transistor Td1, and the load transistor Ta1 are serially connected and together constitute a first-stage source follower circuit. Likewise, the output transistor Td2 and the load transistor Ta2, and the output transistor Td3 and the load transistor Ta3 are respectively, serially connected to constitute second and third-stage source follower circuits.
The gate of the output transistor Td1 of the first-stage source follower circuit is connected to a floating diffusion region FD. The first to third-stage source follower circuits are serially connected, so that the source potential of the output transistor Td3 of the third-stage source follower circuit is extracted as an output signal VOUT of the solid state image capturing element.
A channel region 12 of the horizontal transfer section 10h is formed in a P-well 13 which is formed in one major surface of the horizontal transfer section 10h by diffusing P-type dopants in an N-type semiconductor substrate. Here, the P-well 13 receives a ground potential VGND, while the N-type semiconductor substrate receives a potential of about 5 to 10 V.
An element region 18 on the channel region 12, where a reset transistor Tr is to be formed, is formed continuous from the channel region 12. Regions for a drain and a source of the reset transistor Tr contain N-type dopants diffused therein, respectively forming a floating diffusion region FD and a reset drain region RD.
On the channel region 12, via an insulating film, a plurality of transfer electrodes 14a, 14b are arranged in parallel to one another. An output control electrode 16 is also arranged in parallel to the transfer electrodes 14a, 14b. The transfer electrodes 14a, 14b receive a transfer clock φH, in synchronism with which information charge is transferred along the channel region 12 to the output control electrode 16. The output control electrode 16 receives a constant output control voltage VOG, at which time the information charge is output through a channel formed beneath the output control electrode 16 to the floating diffusion region FD.
In the element region 18, a reset electrode 20 is formed via an insulating film so as to bridge the floating diffusion region FD and the reset drain region RD, whereby the reset transistor Tr is completed. The floating diffusion region FD is connected to a source wire 22, while the reset drain region RD is connected to a drain wire 24.
The information charge having been output to the floating diffusion region FD upon application of the output control voltage VOG is stored therein, and converted into a voltage value. The voltage value of the floating diffusion region FD is extracted through the source wire 22.
A drain voltage VRD is applied to the drain wire 24 and a reset clock φR is applied to the reset electrode 20 to thereby turn on the reset transistor Tr. Thereupon, the information charge stored in the floating diffusion region FD is output via the reset drain region RD into the drain wire 24.
An element region 26 where the first-stage source follower circuit is to be formed is formed on the semiconductor substrate, separated from the element region 18 by a predetermined distance. Further, an element region 28 where the second-stage source follower circuit is to be formed and an element region 30 where the third-stage source follower circuit is to be formed are similarly formed, separated from the other regions by a predetermined distance.
The element regions 26, 28, 30 are formed in P-wells which are formed by diffusing P-type dopants in one major surface of an N-type semiconductor substrate. N-type dopants are doped into the element region 26 so that a drain region Dd1 and a source region Sd1 of an output transistor Td1 and a drain region Da1 and a source region Sa1 of a load transistor Ta1 are formed. Likewise, N-type dopants are doped into the element regions 28, 30 to form drain regions Dd2, Da2, D3, Da3 and source regions Sd2, Sa2, Sd3, Sa3.
The source wire 22 extends to the element region 26 and arranged, via an insulating film, so as to bridge the drain region Dd1 and the source region Sd1, while constituting a gate electrode of the output transistor Td1. The source region Sd1 of the output transistor Td1 and the drain region Da1 of the load transistor Ta1 are connected to each other via a source wire 32. The source wire 32 extends to the element region 28 and is arranged, via an insulating film, so as to bridge the drain region Dd2 and the source region Sd2, while constituting a gate electrode of the output transistor Td2. Likewise, a source region Sd2, a drain region Da2, and a gate electrode of the output transistor Td3 are connected to one another via a source wire 34 of the output transistor Td2. A source region Sd3 and a drain region Da3 are connected to each other via a source wire 36. The source wire 36 serves as an extraction wire through which an output signal VOUT is extracted from the solid state image capturing element.
A gate electrode 38 is arranged via an insulating film on the drain regions Da1, Da2, Da3 and the source regions Sa1, Sa2, Sa3 of the load transistors Ta1, Ta2, Ta3, and the gate electrode 38 receives a common gate potential VGG. Further, the drain regions Dd1, Dd2, Dd3 are connected to one another via a drain wire 40 and receive a common power source potential VDD, while the source regions Sa1, Sa2, Sa3 are connected to one another via a ground wire 42 and maintained at a ground potential VGND.